A finFET includes a narrow source-channel-drain region (the fin) around which is formed a gate. Activation of the gate, source and drain facilitates current drivability in the channel between the source and the drain, thereby facilitating operation of the finFET. Defects in the channel regions of the fins, such as dislocation and stacking fault-like defects, can arise when punch through stop (PTS) implant is performed. Moreover, during reactive ion etching (RIE) of the fins, the positive channel field-effect transistor (pFET) fins end up being smaller than the negative channel field-effect transistor (nFET) fins due to the faster etch rate of the pFET fins formed of silicon germanium (SiGe). Further, punch through leakage is a main component of off-state leakage in bulk finFETs, and it is usually suppressed by forming various punch through stop liners. The punch through is a leakage current between the source and drain in a transistor, so that it is more vulnerable in a short channel device where the distance between source and drain is short. That is, the closer the distance, the larger punch through leakage current. Various liners, such as silicon nitride (SiN), silicon dioxide (SiO2)/silicon nitride (SiN), and SiO2/siliconborocarbonitride (SiBCN) have been used, but can affect device performance.
A need therefore exists for methodology enabling elimination of the PTS implant, prevention of channel damage, elimination of a lithography step to simplify integration, improved nFET and pFET short channel (SC) performance, and better gap fill friendly integration than borosilicate glass (BSG) and phosphosilicate glass (PSG) schemes and the resulting devices.